Latency and Clock Recovery Performance in a Dante System, part one (Ultimo)

Introduction

Two shipping dante audio io units were connected as per the diagram below. The devices were 100mbit devices utilising the Ultimo chip. Both links were 100mbit even though the switch used (extreme summit) was a gigabit switch.

An investigation into the latency and clock recovery performance was undertaken.

Dante Controller latency setting

The 'Device Latency' (dante terminology, that doesn’t equate to AVB terminology) was set to 1ms (the minimum allowed by the dante controller for 100mbit devices):

A stereo connection was made from one device to the other using the dante controller, and the reported ‘latency’ shown in the receiver device was 437uS (peak):

A click track was applied to the sender device's analogue input (L) and the input signal was scoped, along with the output of the receiver device (analogue out L). The measured latency (including all ADC/DAC latencies) was 1.529ms:

Subtracting the 1ms 'network latency' from the total measured latency reveals a device latency (sender plus receiver) of 529uS. This assumes that the network latency doesn’t include any device latency, but we should not assume such things! Let's investigate further.

The units are opened up, and probes are attached to the i2s data lines going from ADC to Ultimo in the sender unit, and from the Ultimo to DAC in the receiver unit. This allows us to measure the i2s->i2s latency:

Trying to identify features in the ADC noise on the i2s data line is not trivial, but in the image above we have correlated the input and output signals and can see that the latency is 998.98uS (about 1ms). This is interesting, because AVB systems separate network latency (the actual latency of the network) with device latency, whereas Dante seems to include some of the device latency (from/to the i2s interface) in the network latency. To get a clearer measurement we can start a capture and pull the ADC output to ground:

This way it's easy to measure the latency (avoid any runt pulse when making the connection to ground that doesn't make it through to the follower). 997uS is measured this time. It's curious that we don't measure exactly 1ms. I wonder if the output is even sample aligned, let alone phase aligned.

We repeat the test a few times, sometimes rebooting the leader, sometimes the follower, sometimes both. An unexpected variation in the i2s->i2s latency is observed. In this capture (following a reboot of the follower) the measured latency is 1007uS

In this capture (following a reboot of the leader) the measured latency is 1015uS

Over several (6) captures we measure latency in the range 997 to 1015, with a delta of 18uS. Is it a coincidence that the period of a 48kHz clock is about 20uS? Perhaps not. Could it be that this Ultimo based solution does not manage to phase align the recovered clock in the follower?

Time to check the clock recovery...

Clock Recovery and FSCLK phase

We investigate the accuracy and responsiveness of the clock recovery system. Probing the FSCLK on both the clock sender (yellow) and clock follower (purple) revealed that, as suspected, the FSCLKs are not always in phase. Usually (at least eight out of ten times) the clocks syntonised but with an arbitrary phase offset. In this capture the phase is about 5/6ths of the period out. Yellow trace is the clock leader, purple is the follower.

Turning on infinite persist we can see that the measured wander (measured over about 5 minutes) was about +-250ns.

Furthermore, the time from clock negotiation completion (where the devices agree on which device will be clock leader) to the clocks being steady takes about 45 seconds:

Both devices are powered on at the start of the video. At about 20s the devices have negotiated the leader, the follower has switched over and clock recovery has started. Note that at this point (when the follower has begun clock recovery) the sync status light of the follower and the sync status in the Dante Controller both show 'synced' as the status, although by Sienda/AVB standards the clocks are far from synced at this point! At about 1:05 the frequency of the follower could be considered matched.

Conclusions

The Ultimo based solution under test did not phase align the FSCLKs of the leader and follower. This lead to a variable latency +-9uS around the configured 1ms latency, and unaligned playback of the audio.

With this setup the 'latency' configured in the Dante Controller is the i2s->i2s latency, NOT the network latency as understood in AVB systems (see Latency in AVB Systems.) Therefore when comparing latencies between AVB systems and Dante systems this difference should be understood and accounted for.

The results and measurements obtained in this investigation may not be representative of all Dante systems. Results of investigation into a Broadway based gigabit Dante system (for comparison) can be found here.