Latency and Clock Recovery Performance of the Sienda TSN Stack Library on an STM32 based device

Introduction

Two STM32 boards running a Sienda firmware and the Sienda TSN Stack Library were connected as per the diagram below. The boards were 100mbit devices utilising the STM32H745. Both links were 100mbit even though the switch used (extreme summit) was a gigabit switch.

An investigation into the latency and clock recovery performance was undertaken.

Hive controller latency setting

The talker stream presentation time was set to 1ms in the Hive AVB controller:

A stereo connection was made from one device to the other using the Hive controller, and the reported ‘accumulated latency’ shown in the listener device was 784uS. This includes the latency of the embedded switches on both the Talker and Listener devices. As this latency is an 802.1Q accumulated latency it is a the minimum value that can be used for the talker presentation time to ensure the guaranteed delivery that AVB provides.

The device has a Talker input latency (from i2s interface to network interface) of 375uS, and a Listener output latency (from presentation time to i2s interface) of 250uS. Thus, with the presentation time offset set to 1ms, we would expect the i2s->i2s latency to be:

total latency = Talker input latency + presentation time offset + Listener output latency
              = 375 + 1000 + 250 uS
              = 1625 uS
              = 1.625 ms

Probes were attached to the i2s data lines going into the Talker device, and from the Listener device. The measured i2s->i2s latency is 1625.028uS:

Clock Recovery and FSCLK phase

Probing the FSCLK on both the Talker (yellow) and Listener (purple) reveals the exceptional performance of the Sienda clock recovery process. Given a Listener FSCLK that is 180deg out of phase with the Talker, the clocks are pulled into perfect phase alignment in under 2.5 seconds:

Waiting for the Listener FSCLK to freewheel to slightly over 180deg out of phase shows that the clock recovery pulls to the nearest frame, again in under 2.5s:

Turning on infinite persist we can see that the measured wander (measured over one hour) was about +-25nS.

Conclusions

Latency in an STM32 based TSN end-station running the Sienda TSN Stack Library is low, deterministic, and guaranteed by the AVB standards.

The Sienda Clock Recovery process is fast, efficient and accurate.